中文名: 王牌設計實現工具英文名: Actel Designer資源格式: 光盤鏡像版本: v7.2發行時間: 2006年地區: 美國簡介:
未通過安全和安裝測試，使用後果自負與本論壇無關
軟件版權歸原作者及原軟件公司所有，如果你喜歡，請購買正版軟件
注：此鏈接下載轉自：TLF論壇
程序語言： 英文
軟件分類： 國外軟件 / 免費版 / 輔助設計
文件大小： 1CD 258.4MB
評價星級：
適用平台： /98/Me/NT/2000/XP/.Net/
Actel Designer 7.2 (王牌設計實現工具):
ACTEL Designer v7.2－專業的FPGA器件開發軟件，是一個能使FPGA的系統性能提高15％的布局工具。
Designer 是Actel的王牌設計實現工具套件。使用你喜歡的前端工具完成設計輸入和功能驗證後,導入網表就能完成物理實現: 約束管理, 布局布線, 時序及功耗分析, 器件編程。
Designer 軟件對所有的Actel的FPGA設器件提供易用的和靈活的解決方案。它使設計者能即插即用地使用業內領先的EDA工具, 如來自Synplicity, Mentor Graphics, Synopsys, Cadence,Magma Design Automation和其它在EDA領域頂尖廠商的軟件。Designer的高級布局布線算法可以滿足今天不斷增長的復雜設計和密度的需要。建立在Designers工具內部的建築專業技術使用戶可以建立最佳的設計。ActelDesigner軟件界面提供圖形化和腳本流，以便適應你的設計環境。圖形設備優化可以通過MultiView Navigator (MVN)和定時接口來實現。這些接口提供給專業用戶最大的靈活性去驅動Place-and-route工具，以快速完成定時關閉。
以上圖片文字介紹來自E維軟件資訊網
如果暫時無源請耐心等待
代碼 安圯
槽圯
?圹圯
? 卟咣圹? ?
圹圯
鞍 圹草
苘苘茌鄄?圹圹圹圮苘?
苘膊圹圹圹圯??苓圹圹圹圹圹?曹?
鞍 苒圹圹圹圹圹圹圹蒇圹坜圹圹圹圹?圹圹膊苘 ?
鞍 苒圹圹圹圹圹圹圹圹鄄圹圹圹圹圹圹苒圹圹圹膊圮
安 圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹鄄圹?
安 槽圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹鄄鞍??
安 槽圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圯 ?
安?槽圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹?
槽 圹膊圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹?
安?圹膊膊槽圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹 ?
槽 鄄膊膊膊圹圹圹圹圹圹圹圹圹圹圮 咿咣槽圹圹圹圹圹圹圹?鞍
安 卟舶膊膊槽圹圹圹圹圹圹圹圹圹甙 圹圹圹圹圹圹圹膊槽??
?圹鞍鞍膊槽膊膊圹圹圹圹圹圹圮槽?槽苒圹圹圹圹圹膊圹圹?舶
?郯? 鞍膊槽圹鄄槽圹圹圹圹圹圹圹圹槽圹圹圹膊槽圹圹?茌 鄄?
薨? 安槽圻哌圹圹鄄膊圹圹哌卟圹鄄哌哌哌哌 ? 苒 苒舶
? 舶 鞍槽? ? ?苘草 安圹圹? ? ? ?佰?鄄?
安 郯 佰圹? ? 圹舶 槽圹圹圮 ? 安圹 鄄?
安? 鞍 鞍圹圹? ? 策?苒圹鄄圹圹? ? 安圹? 郯
鞍安圮 鞍 槽圹圹? ? ?膊圹圹? 圹圹圮 安槽圹圯 舶
鞍膊圮 捋圹圹圹圮? 苘苒圹圹郯 槽圹圹圮苒圹圹圹鄄 ?
苘膊圹?槽圹圹圹圹圹圹槽圹鄄郯 ? 槽圹圹圹圹圹圹??
? ?苘苘苘 槽圹圹圹圻咣圹圹圹圹? 苘 苒圹圹圻哌咣? ?
圹圮圹哌卟槽圮? 哌哌? 圹圹圹圹圹圹圹圹圹圹圯 ?
圹? 鞍鞍膊膊圮 ? ? 捋圹圹圹圹圹圹圹圹圹圹 ?? ?
苒圹 鞍 鞍鞍膊圹 敗苘?圹槽鄄圹圹圹圹槽鄄圹槽蒇圯? 苘苓
圹?咣? 鞍槽圹圹圹策哌 卟圹槽圹槽鄄圹鄄圹策甙? 甙 哌哌膊圮? ?
圹?咣苓圮? 苒圻鄄圹?? 捋?苘哌甙哌 斑哕苘捋廁草 ? ? 哌槽苘
圮 咣鞍圹苒圻鞍槽? 槽捋圯槽蒇草圹蒉鄄斑?甙 ? 卟圮
圹苓鞍槽圻 鞍安槽?? ?苓?卟 圹?槽 哌 ? 咣?
哌圹槽甙鞍安槽圻 鞍 圹草 ? 懿圮
苒圹圹哌哌?鞍? ? 咣圯 ? 哌
鞍鞍? ?苒圹圮 圯 
苘苘圻哌哌圮苘 ?圹?圯捋 ?捋 ? 苓圮
苘圻?苘苘圹圮苘 哌咣苘?槽  圹?苒?? ? 苒
苘圻?苘苘圹圮苘 哌咣苘?槽  圹?苒?? ? 苒
?苘苒圹圹圹圹圹圹鄄?哌?捋? ?苘鄄? 苘苒哌?苘圻 ?
苒圹圹槽捱咣圹圹圹圹圹圹圮?圹圮 咣圹?苓 苘圻哌 苘苒圹圻 苒
圹鄄哌 ?苘苘 卟圹圹鄄圹圹?槽圹圮 ?苒圮圻 苘圹圹圹鄄?苒? ? 
捋圻 ? ? 卟圹 圹圹膊 哌哌?圹圹圹圹苘 哌 懿槽圹圹圹圹圮?哌圮苘苒 捋 ?
咣?卟?? 安圹 圹圹鄄 ? ?圹圹鄄哌圹圹苻槽圹圻膊圹圹圹圹圮?哌 苘槽?
蒇? ? 鞍槽 苒圹圹 ? 荥 槽圹圹 ? 哌圮咣圹 槽圹鄄哌圮圹圹圹圹圹?馨
蒇 ? 安?圹圹圹 ?草 懿圹圹? 懿?圹圮咣?圹圹圮 ? 膊圹圹策 鄄?
? 安?圹圹圹 ?咣圹圹圹圹苘 ? 槽圹??圹圹鄄 ? ?捱圻 苘圻
? ? 安?圹圹圹 ? 咣圹圹圹鄄曹苒圻圻 ?圹圹膊 苘? ??
? 安?圻圹鄄 ?  圹圹圹哌圹圹圮曹 ?甙咣鄄圹圻 ? ?
? 安?馨苒圹 圯 ?圹圹圹 ? 哌圹圹圮 圮圹圹? ? ?
安槽 圹圻鄄 圹苘?甙咣圮 曹苘?圹圹圯 圹圻圹 苓? 苘? ?
鞍槽圹 槽圹鄄 ? 苘 圮圹膊 苘苘?膊圻圯 圹圹鄄 苘圹圹圹膊?咣馨
苘圻哌 苘 圹圹膊圹策哌 圹槽圹圹圹圹圹圹圹蒉圹圹膊圹圹圹圹圹圹曹 咣?
苓?苘圹圹哌哌?苘苘 苘圹圹圻哌 苘苘 哌咣圯捋圹圹哌?苘?咻?哌圹?卟
?苒圻哌鞍 ? 哌?圻 圹圻? 哌哌 哌哌 哌哌? 哌? ? ? 鞍咣??
?圹甙? 懿圮 ?圹?* THE BiTTER END * 懿? ? 稗圯
捋莅 ? 哌 ? 哌圮? presents ?苘? 苓
哕 佰? 圹舶 
唼 苘苒圻? 圻圹苘苓
圹圮 圹哌 Actel Designer v7.2 SPA 哌圹 苒圻
?圹蒇 坜圹?
? 鄄? Actel 槽郯
?苒? 斑圮
苘圻 咣苘?
苘圹圻? SUPPLiER.... TEAM TBE DATE ... 03.08.2006 斑圹圮?
懿圹圻? CRACKER .... TEAM TBE TYPE ... util 斑圹鄄?
薏圹郯 PROTECTiON . some OS ..... win 佰圹草
卟圹馨? LANGUAGE ... english SiZE ... 1 CDs 鞍苒鄄?
斑槽圮鞍 ?苒鄄甙
?哌圹苘鞍 URL www.actel.com 鞍苘圹哌 ?
?哕?哌圹苘 苘圹哌 苘??
?苘圹?安圹圹苘? * RELEASE NOTES * 苘苒圹鄄?咣圮??
苒圻?苘圹哌?哌哌哌? ============= 哌哌哌?斑咣圮?哌槽?
圹舶 苒甙? 鞍咣?安圹
捋鄄?卟苘? 哕懿?安圹?
槽圮 佰 ? 敗圹?
斑咣圮? ? ? 苘槽哌
? 哌哌 Designer is Actel s powerful physical 哌哌?
? implementation software tool suite. After ? ?
? completing design entry and functional ? ?
? verification using your favorite front-end ? ?
? design tools, simply import the resulting ?
? netlist into Designer to complete the ?
? constraints management, place-and-route, ?
? timing and power analysis, and ?
? programming. ?
? ?
? Actel s Designer software offers an ?
? easy-to-use and flexible solution for all ?
? Actel FPGA devices. It gives you the ?
? flexibility to plug and play industry-leading ?
? EDA tools from partners such as ?
? Synplicity, Mentor Graphics, Synopsys, ?
? Cadence, Magma Design Automation, and ?
? many other top names in the EDA field. ?
? ?
? Designer s advanced place-and-route ?
? algorithms accommodate the needs of ?
? today s increasingly complex design ?
? requirements such as Fusion mixed-signal ?
? and CoreConsole/Libero IDE generated ?
? Actel ARM7-CoreMP7 system-on-chip ?
? designs. The architectural expertise built ?
? into Designer s tools enables you to ?
? create fully optimized designs. Actel s ?
? Designer software interface offers both ?
? graphical and scriptable flows in order to ?
? accommodate your design environment. ?
? Graphical device optimization and ?
? constraints management can be done ?
? through the MultiView Navigator MVN , ?
? SmartTime, and Timer interfaces. These ?
? interfaces provide you maximum ?
? flexibility to drive the place-and-route ?
? tools and quickly achieve timing closure. ?
? ?
懿哌? 苓卟?
? 咣? 苒? ?
敗 哌圮? 苘圻? 馨
安圮? 安圹苘? * iNSTALLATiON NOTES * 苘苒鄄? 苘鄄?
苒哌 苘圹? 哌哌? =============
安圯
槽圯
?圹圯
? 卟咣圹? ?
圹圯
鞍 圹草
苘苘茌鄄?圹圹圹圮苘?
苘膊圹圹圹圯??苓圹圹圹圹圹?曹?
鞍 苒圹圹圹圹圹圹圹蒇圹坜圹圹圹圹?圹圹膊苘 ?
鞍 苒圹圹圹圹圹圹圹圹鄄圹圹圹圹圹圹苒圹圹圹膊圮
安 圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹鄄圹?
安 槽圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹鄄鞍??
安 槽圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圯 ?
安?槽圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹?
槽 圹膊圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹?
安?圹膊膊槽圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹圹 ?
槽 鄄膊膊膊圹圹圹圹圹圹圹圹圹圹圮 咿咣槽圹圹圹圹圹圹圹?鞍
安 卟舶膊膊槽圹圹圹圹圹圹圹圹圹甙 圹圹圹圹圹圹圹膊槽??
?圹鞍鞍膊槽膊膊圹圹圹圹圹圹圮槽?槽苒圹圹圹圹圹膊圹圹?舶
?郯? 鞍膊槽圹鄄槽圹圹圹圹圹圹圹圹槽圹圹圹膊槽圹圹?茌 鄄?
薨? 安槽圻哌圹圹鄄膊圹圹哌卟圹鄄哌哌哌哌 ? 苒 苒舶
? 舶 鞍槽? ? ?苘草 安圹圹? ? ? ?佰?鄄?
安 郯 佰圹? ? 圹舶 槽圹圹圮 ? 安圹 鄄?
安? 鞍 鞍圹圹? ? 策?苒圹鄄圹圹? ? 安圹? 郯
鞍安圮 鞍 槽圹圹? ? ?膊圹圹? 圹圹圮 安槽圹圯 舶
鞍膊圮 捋圹圹圹圮? 苘苒圹圹郯 槽圹圹圮苒圹圹圹鄄 ?
苘膊圹?槽圹圹圹圹圹圹槽圹鄄郯 ? 槽圹圹圹圹圹圹??
? ?苘苘苘 槽圹圹圹圻咣圹圹圹圹? 苘 苒圹圹圻哌咣? ?
圹圮圹哌卟槽圮? 哌哌? 圹圹圹圹圹圹圹圹圹圹圯 ?
圹? 鞍鞍膊膊圮 ? ? 捋圹圹圹圹圹圹圹圹圹圹 ?? ?
苒圹 鞍 鞍鞍膊圹 敗苘?圹槽鄄圹圹圹圹槽鄄圹槽蒇圯? 苘苓
圹?咣? 鞍槽圹圹圹策哌 卟圹槽圹槽鄄圹鄄圹策甙? 甙 哌哌膊圮? ?
圹?咣苓圮? 苒圻鄄圹?? 捋?苘哌甙哌 斑哕苘捋廁草 ? ? 哌槽苘
圮 咣鞍圹苒圻鞍槽? 槽捋圯槽蒇草圹蒉鄄斑?甙 ? 卟圮
圹苓鞍槽圻 鞍安槽?? ?苓?卟 圹?槽 哌 ? 咣?
哌圹槽甙鞍安槽圻 鞍 圹草 ? 懿圮
苒圹圹哌哌?鞍? ? 咣圯 ? 哌
鞍鞍? ?苒圹圮 圯 
苘苘圻哌哌圮苘 ?圹?圯捋 ?捋 ? 苓圮
苘圻?苘苘圹圮苘 哌咣苘?槽  圹?苒?? ? 苒
苘圻?苘苘圹圮苘 哌咣苘?槽  圹?苒?? ? 苒
?苘苒圹圹圹圹圹圹鄄?哌?捋? ?苘鄄? 苘苒哌?苘圻 ?
苒圹圹槽捱咣圹圹圹圹圹圹圮?圹圮 咣圹?苓 苘圻哌 苘苒圹圻 苒
圹鄄哌 ?苘苘 卟圹圹鄄圹圹?槽圹圮 ?苒圮圻 苘圹圹圹鄄?苒? ? 
捋圻 ? ? 卟圹 圹圹膊 哌哌?圹圹圹圹苘 哌 懿槽圹圹圹圹圮?哌圮苘苒 捋 ?
咣?卟?? 安圹 圹圹鄄 ? ?圹圹鄄哌圹圹苻槽圹圻膊圹圹圹圹圮?哌 苘槽?
蒇? ? 鞍槽 苒圹圹 ? 荥 槽圹圹 ? 哌圮咣圹 槽圹鄄哌圮圹圹圹圹圹?馨
蒇 ? 安?圹圹圹 ?草 懿圹圹? 懿?圹圮咣?圹圹圮 ? 膊圹圹策 鄄?
? 安?圹圹圹 ?咣圹圹圹圹苘 ? 槽圹??圹圹鄄 ? ?捱圻 苘圻
? ? 安?圹圹圹 ? 咣圹圹圹鄄曹苒圻圻 ?圹圹膊 苘? ??
? 安?圻圹鄄 ?  圹圹圹哌圹圹圮曹 ?甙咣鄄圹圻 ? ?
? 安?馨苒圹 圯 ?圹圹圹 ? 哌圹圹圮 圮圹圹? ? ?
安槽 圹圻鄄 圹苘?甙咣圮 曹苘?圹圹圯 圹圻圹 苓? 苘? ?
鞍槽圹 槽圹鄄 ? 苘 圮圹膊 苘苘?膊圻圯 圹圹鄄 苘圹圹圹膊?咣馨
苘圻哌 苘 圹圹膊圹策哌 圹槽圹圹圹圹圹圹圹蒉圹圹膊圹圹圹圹圹圹曹 咣?
苓?苘圹圹哌哌?苘苘 苘圹圹圻哌 苘苘 哌咣圯捋圹圹哌?苘?咻?哌圹?卟
?苒圻哌鞍 ? 哌?圻 圹圻? 哌哌 哌哌 哌哌? 哌? ? ? 鞍咣??
?圹甙? 懿圮 ?圹?* THE BiTTER END * 懿? ? 稗圯
捋莅 ? 哌 ? 哌圮? presents ?苘? 苓
哕 佰? 圹舶 
唼 苘苒圻? 圻圹苘苓
圹圮 圹哌 Actel Designer v7.2 SPA 哌圹 苒圻
?圹蒇 坜圹?
? 鄄? Actel 槽郯
?苒? 斑圮
苘圻 咣苘?
苘圹圻? SUPPLiER.... TEAM TBE DATE ... 03.08.2006 斑圹圮?
懿圹圻? CRACKER .... TEAM TBE TYPE ... util 斑圹鄄?
薏圹郯 PROTECTiON . some OS ..... win 佰圹草
卟圹馨? LANGUAGE ... english SiZE ... 1 CDs 鞍苒鄄?
斑槽圮鞍 ?苒鄄甙
?哌圹苘鞍 URL www.actel.com 鞍苘圹哌 ?
?哕?哌圹苘 苘圹哌 苘??
?苘圹?安圹圹苘? * RELEASE NOTES * 苘苒圹鄄?咣圮??
苒圻?苘圹哌?哌哌哌? ============= 哌哌哌?斑咣圮?哌槽?
圹舶 苒甙? 鞍咣?安圹
捋鄄?卟苘? 哕懿?安圹?
槽圮 佰 ? 敗圹?
斑咣圮? ? ? 苘槽哌
? 哌哌 Designer is Actel s powerful physical 哌哌?
? implementation software tool suite. After ? ?
? completing design entry and functional ? ?
? verification using your favorite front-end ? ?
? design tools, simply import the resulting ?
? netlist into Designer to complete the ?
? constraints management, place-and-route, ?
? timing and power analysis, and ?
? programming. ?
? ?
? Actel s Designer software offers an ?
? easy-to-use and flexible solution for all ?
? Actel FPGA devices. It gives you the ?
? flexibility to plug and play industry-leading ?
? EDA tools from partners such as ?
? Synplicity, Mentor Graphics, Synopsys, ?
? Cadence, Magma Design Automation, and ?
? many other top names in the EDA field. ?
? ?
? Designer s advanced place-and-route ?
? algorithms accommodate the needs of ?
? today s increasingly complex design ?
? requirements such as Fusion mixed-signal ?
? and CoreConsole/Libero IDE generated ?
? Actel ARM7-CoreMP7 system-on-chip ?
? designs. The architectural expertise built ?
? into Designer s tools enables you to ?
? create fully optimized designs. Actel s ?
? Designer software interface offers both ?
? graphical and scriptable flows in order to ?
? accommodate your design environment. ?
? Graphical device optimization and ?
? constraints management can be done ?
? through the MultiView Navigator MVN , ?
? SmartTime, and Timer interfaces. These ?
? interfaces provide you maximum ?
? flexibility to drive the place-and-route ?
? tools and quickly achieve timing closure. ?
? ?
懿哌? 苓卟?
? 咣? 苒? ?
敗 哌圮? 苘圻? 馨
安圮? 安圹苘? * iNSTALLATiON NOTES * 苘苒鄄? 苘鄄?
苒哌 苘圹? 哌哌? =============