中文名: Altera (FPGA)電子設計軟件英文名: Altera Quartus II資源格式: 光盤鏡像版本: v9.1發行時間: 2009年11月03日制作發行: Altera Corporation地區: 美國語言: 英文簡介:


軟件類型：行業軟件
軟件性質：無插件破解軟件
操作系統：Windows Vista (32/64 bit) and Windows XP (32/64 bit)
官方網站：http://www.altera.com/products/software/sfw-index.jsp
2009年11月3號，北京—— Altera公司 (NASDAQ: ALTR)今天宣布推出 Quartus® II軟件9.1 ——在CPLD、FPGA和HardCopy® ASIC設計方面，業界性能和效能最好的軟件。與以前的軟件版本相比，Quartus II軟件9.1新特性和增強功能將編譯時間縮短了20％，編譯時間比競爭高密度40-nm和65-nm設計仍然快2到3倍。軟件新特性是快速重新編譯，對於較小的設計改動，這一特性大大縮短了編譯時間，而且還支持Altera最新發布的 Cyclone®IV FPGA 。
Quartus II 軟件9.1建立在Altera設計軟件一直保持的效能優勢基礎上。對於高端FPGA，軟件實現了業界最快的編譯時間，過去5年中，編譯時間平均每年縮短 20％。最新版軟件編譯時間上的優勢來自於更高效的布局布線算法，更好的多處理器支持以及更快的時序驅動綜合等。
快速重新編譯實現了更快的設計迭代
快速重新編譯新特性使Quartus II軟件能夠進一步縮短設計編譯時間。運行全編譯之後，進行小的工程變更(ECO)設計修改時，快速重新編譯特性大大提高了設計人員的效能，與再次運行設計全編譯相比，編譯時間平均縮短了50％。在時序逼近過程中，快速重新編譯保留上次設計改動期間的關鍵時序，明顯提高了設計人員的效率。
擴展了對新Cyclone IV FPGA的器件支持
Quartus II 設計軟件9.1支持三種最小的Cyclone IV GX器件，Quartus II設計軟件9.1 SP1將支持其他的Cyclone IV器件。如果需要了解今天進行的Cyclone IV系列新聞發布，請訪問 www.altera.com.cn/corporate/news_room/releases/2009/products/nr-cyclone-iv.html 。這一版本的Quartus II軟件還支持 Stratix® IV E EP4SE820 FPGA——業界密度最高的820K邏輯單元(LE) FPGA。為Altera最新FPGA系列提供支持使客戶能夠馬上迅速開始最新的Cyclone和Stratix FPGA設計。
Quartus II軟件9.1的其他特性包括：
* 漸進式編譯非矩形分區——非矩形區域使用戶能夠建立更緊湊、更高效的平面布局，更容易實現高質量標准。這一新特性為用戶提供了更簡單方便的介面，在設計劃分過程中進行精確控制。
* 增強SSN分析器工具——這一工具增加了對Arria® II GX FPGA和Stratix IV GX FPGA的支持，在引腳分配期間，及時反饋可能出現的同時開關噪聲(SSN)違規問題。
* 新的擴展IP基本包——三個新存儲器控制器支持RLDRAM II、QDRII / II+和DDR1/2/3，該基本包增加到14個知識產權(IP)內核。
* 初步支持VHDL 2008——Quartus II軟件提供更靈活的語言結構，使用戶能夠開發可重用的代碼結構，繼續保持了該軟件在語言支持上的領先優勢。
* Nios® II處理器——現在提供的“/e”型Nios II軟核處理器不再需要許可費用。這一版本還標志著Nios II軟件開發工具開始支持Eclipse，提高了軟件開發效率。
* 擴展OS支持——現在可以支持Linux SUSE 10。
關於Quartus II軟件9.1特性的其他信息，請訪問 www.altera.com.cn/q2whatsnew 。
Altera軟件、嵌入式和DSP市場資深總監Chris Balough評論說：“面臨預算更緊張、研發資源減少以及設計周期縮短等挑戰，當今的設計團隊因此一直在尋找提高效能的好方法。Quartus II軟件越來越強的效能優勢使我們的客戶能夠更迅速的將其FPGA推向市場，同時降低了工程開支。”
價格和供貨信息
現在可以下載 Quartus II軟件9.1訂購版和免費的網絡版。Quartus II軟件訂戶可以收到ModelSim Altera入門版軟件，以及IP基本包的全部許可，它包括14個Altera最流行的IP (DSP和存儲器)內核。一個節點鎖定的PC許可的年度軟件訂購價格是2,495美元，可以從 Altera eStore 或者授權分銷商那裡購買。
Altera簡介
Altera®的可編程解決方案幫助系統和半導體公司快速高效地實現創新，突出產品優勢，贏得市場競爭。請訪問www.altera.com ，或者www.altera.com.cn ，了解Altera FPGA、CPLD和ASIC的詳細信息。
What's new in Quartus II design software version 9.1?
Quartus® II software version 9.1 delivers the #1 performance and productivity for FPGA, CPLD, and HardCopy® ASIC designs. This new release supports Altera's new lowest cost, lowest power FPGA family—Cyclone® IV GX FPGAs with integrated 3.125-Gbps transceivers. The Cyclone IV GX FPGA family is targeted to high-volume, cost-sensitive applications, enabling you to meet increasing bandwidth requirements while lowering costs. Version 9.1 further extends Quartus II software's productivity advantage by delivering 20 percent overall compile time reduction over Quartus II software version 9.0, and maintains 2x to 3x faster compile times than the nearest competitor for high-density 65-nm and 40-nm designs. In addition, the new Rapid Recompile feature in version 9.1 reduces compile times by 50 percent (on average) compared to a full compile when small engineering change order (ECO)-type design changes are made. Finally, this release also supports the largest FPGA in the industry—Stratix® IV E EP4SE820 devices.
New Rapid Recompile for Faster Design Iteration
The new Rapid Recompile feature enhances Quartus II software's ability to further minimize design compilation times. Rapid Recompile maximizes productivity by enabling faster small ECO-type design changes after a full compile, reducing compilation times by 50 percent (on average) versus running another full compile on the design. Rapid Recompile also significantly improves productivity during timing closure by preserving critical timing during late design changes.
Cyclone IV GX FPGA Support
Quartus II software now supports Altera's new generation of low-cost and low-power FPGAs—Cyclone IV GX FPGAs with integrated transceivers. This transceiver variant in the Cyclone IV FPGA family supports mainstream protocols up to 3.125-Gbps with integrated hard PCIe intellectual property (IP) blocks. Compared to Cyclone III FPGAs with external transceivers, Cyclone IV GX FPGAs consume up to 30 percent less total power. Quartus II software version 9.1 offers PowerPlay Power Analysis and Optimization Technology to achieve the lowest power within your power budget. Start your Cyclone IV GX design with Quartus II software and take advantage of the power and cost savings without sacrificing performance.
The Cyclone IV GX EP4CGX15, EP4CGX22, and EP4CGX30 devices are supported (advanced support) in this release. For more information, please visit the Cyclone IV FPGA page. With this latest addition, Quartus II software offers support for all low-cost, mid-range, and high-performance (11.3-Gbps) transceiver FPGAs.
Industry's Fastest Compile Times
Quartus II software version 9.1 continues to deliver the industry's fastest compile times (2X to 3X faster than the nearest competitor for high-density 65-nm and 40-nm designs). Version 9.1 also delivers 20 percent overall compile time reduction over Quartus II software version 9.0 in all design stages. Regardless of which design stage you are at, you will experience faster compile times by upgrading to the latest version 9.1 release. In addition, Quartus II software introduces the new Rapid Recompile feature to extend its leadership in design compilation time.
With version 9.1, you get the following compilation advantages:
* Rapid Recompile for compile-time reduction and timing preservation when making small design changes
* Support for multiprocessors resulting in (on average) 20 percent faster compile times
* Advanced place-and-route algorithms for industry-leading compile times
* Incremental compile support for an additional compile-time reduction of up to 70 percent
Faster Multiprocessor Support with New Parallel Synthesis
Quartus II software is the leader in multi-processor support and is the only FPGA design software that performs parallel processing in all synthesis, place-and-route, static timing analysis, and assembler design stages. Quartus II software also can achieve a 20 percent compilation time saving, on average. In the version 9.1 release, new parallel synthesis support significantly reduces synthesis time for designs with partitions.
Faster Timing-Driven Synthesis
Timing-driven synthesis increases performance of your design by performing synthesis while keeping timing constraints in mind. Version 9.1 delivers an enhanced timing-driven synthesis feature, enabling you to improve design performance in 10 percent less compile time than the previous versions for faster timing closure.
Improved Incremental Compile
Time spent closing timing usually pertains to one or two critical blocks of your design. The incremental compile feature allows you make changes and compile just the critical blocks until timing is closed. This methodology allows you to reduce your compilation times by up to 70 percent compared to a flat compile. Version 9.1 adds more flexibility to close timing and optimize your design with partitions.
Additional Enhancements
* VHDL 2008 Initial Support—Quartus II software maintains its leadership in language support by providing a more flexible and easy-to-use language structure.
* New and Expanded IP Base Suite—Three new and faster memory controllers
* Expanded SSN Analyzer Tool Support—With added support for Stratix IV and Arria® II GX devices, the SSN Analyzer allows you to interactively manage pin assignments and reduce SSN violations, providing faster board design and shorter system-level debug time.
* Non-Rectangular Floorplanning—Non-rectangular regions help create more compact and efficient floorplans, making it easier to achieve quality metrics. Quartus II software version 9.1 helps to create non-rectangular floorplans, which provides more freedom.
* Free Nios II/e Soft Processor—Now includes the lowest-cost Nios II processor core using the fewest FPGA logic and memory resources in the Nios II family.
* Expanded OS Support—Adds SUSE Enterprise 10 support in addition to SUSE Enterprise 9 support.
Device Support
* Stratix IV GX/Stratix IV GT FPGAs—Adds EP4SGX230, EP4SGX180, EP4S40G2, and EP4S100G2 device programming support. New EP4SGX290, EP4S40G5, EP4S100G3, EP4S100G4, EP4S100G5 devices include advanced support.
* Stratix IV E FPGAs—Adds advanced support for the EP4SE820 and the EP4SE230 devices.
* HardCopy III/HardCopy IV ASICs—New HardCopy IV GX compilation support enables design handoff for back-end ASIC processing.
* Arria II GX FPGAs—Adds programming support for EP2AGX65 and EP2AGX45 devices. Removes EP2AGX30 and EP2AGX20 devices from support.
* Removal of Older Families—The ACEXTM 1K, APEXTM 20KC, APEX 20KE, APEX II, FLEX® 6000, FLEX 10K, FLEX 10KA, FLEX 10KE, and HardCopy Stratix device families will be removed from Quartus II software version 9.1 and future releases. The last support for these device families is version 9.0 SP2, which will be available permanently on Altera's Download Center.
Advanced support includes compilation and pin-out support; programming support includes compilation, pin-out, and device programming (POF) support.
引用安裝指南
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█░▌ Type ..... FPGA ▐░█
█░▌ Date ..... 11/2009 ▐░█
█░▌ Size ..... 60x50MB ▐░█
█░▌ OS ....... Windows 32/64bit ▐░█
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█░▌ ░░░▒▒█▌▒▒▒████████████▓░ RELEASE NOTES ░▓████████████▒▒▒▐█▒▒░░░░ ▐░█
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New in this release of Quartus II software, support for Altera's new
Arria II GX FPGAs with cost-optimized, easy-to-use 3.75-Gbps transceivers.
Version 9.0 also adds support for Altera's new Stratix IV GT FPGAs, the
only FPGAs with integrated 11.3-Gbps transceivers. This version also
extends Quartus II software's productivity advantage with the new
simultaneous switching noise SSN Analyzer tool for faster board design
and expanded multi-processor support for faster compiles times.
http //www.altera.com/products/software/sfw-index.jsp
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█░▌ Unrar, burn/mount, install. Check /SPYRAL ▐░█
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